The present invention relates to a semiconductor memory device, and more particularly to techniques which are effective when applied to a semiconductor memory device having bipolar transistors and CMOS-FETs (complementary insulated-gate field effect transistors), this semiconductor memory device being hereinbelow termed a "semiconductor memory device of the bipolar-CMOS type." By way of example, the invention is effectively utilized for a static semiconductor memory device (hereinbelow, termed "S-RAM") of the bipolar-CMOS type, such as a bipolar-CMOS type S-RAM the levels of the input/output signals of which are compatible with those of the signals of ECL (emitter-coupled logic). The bipolar-CMOS type S-RAM is shown in Page 37-39 of NIKKEI ELECTRONICS 1986.12.29 (no. 411).
FIG. 3 shows a block diagram of a semiconductor memory device which was studied by the inventors prior to the present invention. The semiconductor memory device illustrated in the figure is a bipolar-CMOS type S-RAM the periphery of which is capable of signal level compatibility with ECL.
Referring to the figure, the semiconductor memory device includes a memory array 1 in which a large number of memory cells m are arrayed in the shape of a matrix. In the memory array 1, large numbers of word lines L.sub.X and data line pairs L.sub.Y are laid in order to select any desired ones of the memory cells m. All the data line pairs L.sub.Y are connected to a common data line pair L.sub.C through Y select switches 2 respectively corresponding thereto, and the common data line pair L.sub.C is connected to the input terminals of a sense amplifier 3.
Symbol X.sub.S denotes word select signals, which select a desired word line from among the large number of word lines L.sub.X and drive it. In addition, symbol Y.sub.S denotes Y select signals, which select one of the Y select switches 2 and bring it into the "on" state. Thus, any desired memory cell m is selected from among the plurality of memory cells, and as read signals, data stored in the selected memory cell m is supplied therefrom to the sense amplifier 3 through the common data line pair L.sub.C which is pulled up to the side of a positive power source potential V.sub.CC. The supplied read signals are amplified into read signals of predetermined levels by the sense amplifier 3. Thereafter, the read signals are delivered to external data terminals via an input/output buffer circuit or the like though this is not illustrated in the figure.
Each pair of data lines L.sub.Y and the pair of common data lines L.sub.C are respectively pulled up to the side of the positive power source potential V.sub.CC by pull-up circuits 4 and 5 constructed of P-channel MOSFETs (insulated-gate field effect transistors). On the pair of common data lines L.sub.C, there appear the minute read signals which oscillate slightly to the side of a negative power source potential with the positive power source potential V.sub.CC as a reference level. These minute read signals are amplified by the sense amplifier 3.